1. Scalable Computing/Analysis
1.1 Three architecture ?
1.1.1 Shared-Nothing versus Shared-Everything
- Patterns for Distributed or Parallel computing
- big problems, break it down, computing unit
- which pattern to use
trader-off between compute and communication costs
MPP?
1.1.2 Shared-Memory
- single machine, multiple processes
Apply in:
- GPU-based parallel-computing architecture
- Deep Learning
- multiple machines
RDMA (Remote direct memory access)
data-center network
warehouse-scale computing
NUMA?
1.1.3 Shared-Storage
- in 80’s, NFS/DFS/Andrew
- today, SAN/NAS/Virtualized storage
2. Core elements in architecture
架构核心要素,思维导图
Ref Book:
大型网站技术架构
3. Server Architecture
3.1 服务器三大体系结构
Three architecture for business server
- Symmetric Multi-Processing (SMP) 主流服务器架构
对称多处理架构:多个CPU对称工作,无主次或从属关系
1 | Share same physical memory, access to any address takes same time |
- Massively Parallel Processing (MPP)
- 海量并行处理结构: 多个SMP服务器(节点)互联而成
- 完全无共享结构(Share Nothing)
- Thus:扩展能力最好,目前512个节点,数千个CPU
- Non-Uniform Memory Access (NUMA)
- 非一致存储访问结构
- Feature: 多个CPU模块,每个模块多个CPU
- 独立内存,I/O
- 通过互联模块(eg. crossbar switch) 连接和信息交互
- 支持上百个CPU
- Defects:远地内存延时太多
系统性能无法线性增加
MPP vs. NUMA
Criteria | MPP | NUMA |
---|---|---|
节点互联机制 | I/O | inside same physical server |
内存访问机制 | access only local | access to all, remote delays |
Usage | data warehouse, i/o | OLTP, little data, fast processing |
Transitioning from SMP to MPP, the why and the how
3.2 多核系统三大架构
- SMP
- 一个操作系统的实例可以同时管理所有CPU内核,且应用并不绑定某一个内核
- Asymmetric Multi-Processing (AMP)
- 非对称多处理架构
- 每个CPU内核可能运行一个独立的操作系统或同一操作系统的独立实例(instantiation)
AMP vs. SMP
Criteria | AMP | SMP |
---|---|---|
耦合 | 松耦合多CPU系统 | 紧耦合多CPU系统 |
OS | one CPU, one OS | multi CPU, share one OS |
Apply | less | more |
- Bound Multi-Processing (BMP)
- 混合多处理架构
- 一个操作系统的实例可以同时管理所有CPU内核,但每个应用被锁定于某个指定的核心
3.3 补充
Seemingly, SMP(UMA), NUMA and MPP refers to CPU and RAM architecture
And SMP, AMP, BMP refers to CPU and OS architecture
More on 17-09-29:
SMP: multiprocessor computer hardware and software architecture
UMA: a shared memory architecture used in parallel computers
UMA may use bus-based SMP arch or crossbar switches
Intel 用了很牛的技术 SMT (同步多线程),一个CPU同时可以执行两个线程,如双核CPU可以有4个逻辑处理器
SMT(Simultaneous Multi-threading)
Def: Permits multiple independent threads to execute simultaneously on the SAME core.
Weaving together multiple “threads” on the same core
SMT v.s. Hyper Threading
SMT: an architecture feature of some processors
allows multiple thread to issue instructions on each cycle(same time ?)
Hyper-Threading is a specific implementation of SMT.
4 Design of System
4.1 Building block
decomposition and combination
分解和组合
System bus
系统总线
separate producer and consumerRouting
路由
external route: different input –> |dispatch| –> component
internal route: service level, eg.consul, way like pattern matching
Mind data
Identify its ID before reaching Bus, called data normalization/data encapsulation
Queue
A special version of bus + route[optional] + storage ?
amends for the speed collapse of consumer and producerPub/Sub
An candidate for route
Managed by PublisherProtocol
To communicate though bus or queue, we need a protocol to define behaviour.
like an SLA, service level agreement
4.2 vital services
sweeping
代谢
exception close, restart, restore…
eg. supervisor/child process in erlang, supervision tree(like nginx)High Availability
Security
divide into initiative and passive(主动安全与被动安全)
Initiative: authentication/authorization + TLS + encrypt + minimum input/output
Passive: firewall
Overdraft protection
透支保护
auto scaling/back pressure/Service degradation
Reference:
软件设计杂谈